1. Field of the Invention
The present invention relates to high speed, low power comparators.
2. Background Art
Commercialization of the Internet has proven to be a mainspring for incentives to improve network technologies. Development programs have pursued various approaches including strategies to leverage use of the existing Public Switched Telephone Network and plans to expand use of wireless technologies for networking applications. Both of these approaches (and others) entail the conversion of data between analog and digital formats. Therefore, it is expected that analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) will continue to perform critical functions in many network applications.
Because ADCs find uses in a wide variety of applications, design of these circuits has evolved along many paths to yield several distinct architectures, including xe2x80x9cdelta sigma,xe2x80x9d xe2x80x9csuccessive approximation,xe2x80x9d xe2x80x9cpipelined,xe2x80x9d xe2x80x9csubranging,xe2x80x9d xe2x80x9cfolding,xe2x80x9d and xe2x80x9cflash.xe2x80x9d Comparators are the basic building block in each of these designs, and some architecturesxe2x80x94such as pipelined, subranging, folding, and flashxe2x80x94use an array of comparators.
For example, FIG. 1 is a block diagram of an exemplary conventional two-bit flash ADC 100. ADC 100 comprises a first comparator xe2x80x9cAxe2x80x9d 102, a second comparator xe2x80x9cBxe2x80x9d 104, a third comparator xe2x80x9cCxe2x80x9d 106, a priority encoder 108, a first resistor xe2x80x9cR1xe2x80x9d 110, a second resistor xe2x80x9cR2xe2x80x9d 112, a third resistor xe2x80x9cR3xe2x80x9d 114, and a fourth resistor xe2x80x9cR4xe2x80x9d 116. Each of R1 110, R2 112, R3 114, and R4 116 has the same measure of resistance. R1 110, R2 112, R3 114, and R4 116 are connected in series between an analog ground xe2x80x9cVAGxe2x80x9d 118 and a first supply voltage xe2x80x9cVDDxe2x80x9d 120. (Alternatively, analog ground VAG 118 can be replaced by a second supply voltage xe2x80x9cVSSxe2x80x9d.) R1 110 is connected between VAG 118 and a first node xe2x80x9cN1xe2x80x9d 122. R2 112 is connected between N1 122 and a second node xe2x80x9cN2xe2x80x9d 124. R3 114 is connected between N2 124 and a third node xe2x80x9cN3xe2x80x9d 126. R4 116 is connected between N3 126 and VDD 120. In this configuration, the voltage at N1 122 (the reference voltage of comparator A 102) is equal to VDD/4, the voltage at N2 124 (the reference voltage of comparator B 104) is equal to VDD/2, and the voltage at N3 126 (the reference voltage of comparator C 106) is equal to 3VDD/4.
The inverting terminals of comparators A 102, B 104, and C 106 are connected to, respectively, N1, 122, N2 124, and N3 126. An analog signal xe2x80x9cxxe2x80x9d 128 is received at an input 130, which is connected to the noninverting terminals of comparators A 102, B 104, and C 106. A quantized signal is produced at the output terminal of each comparator. Quantized signals xe2x80x9cw1xe2x80x9d 132, xe2x80x9cw2xe2x80x9d 134, and xe2x80x9cw3xe2x80x9d 136 are produced at the output terminals of, respectively, comparators A 102, B 104, and C 106. Each quantized signal has a voltage with a value xe2x80x9cLOWxe2x80x9d or a value xe2x80x9cHIGHxe2x80x9d depending upon whether a corresponding value of the voltage of analog signal x 128 is less than (or equal to) or greater than the voltage at the inverting terminal of the corresponding comparator (i.e., the reference voltage of the comparator). For example, when the value of the voltage of analog signal x 128 is less than or equal to VDD/4, the values of the voltages of w3 136, w2 134, and w1 132 are equal to, respectively, LOW, LOW, and LOW. When the value of the voltage of analog signal x 128 is less than or equal to VDD/2, but greater than VDD/4, the values of the voltages of w3 136, w2 134, and w1 132 are equal to, respectively, LOW, LOW, and HIGH. When the value of the voltage of analog signal x 128 is less than or equal to 3VDD/4, but greater than VDD/2, the values of the voltages of w3 136, w2 134, and w1 132 are equal to, respectively, LOW, HIGH, and HIGH. When the value of the voltage of analog signal x 128 is less than or equal to VDD, but greater than 3VDD/4, the values of the voltages of w3 136, w2 134, and w1 132 are equal to, respectively, HIGH, HIGH, and HIGH.
The output terminals of comparators A 102, B 104, and C 106 are connected to priority encoder 108. Quantized signals w1 132, w2 134, and w3 136 are received by priority encoder 108, which processes them to produce, at an output 138, a two-bit digital signal xe2x80x9cyxe2x80x9d comprising a least significant bit (LSB) signal xe2x80x9cy1xe2x80x9d 140 and a most significant bit (MSB) signal xe2x80x9cy2xe2x80x9d 142.
The skilled artisan will appreciate that, with additional comparators and resistors and by using a priority encoder capable of processing additional quantized signals, flash ADC 100 can be modified so that digital signal y comprises more than two bit signals. Alternatively, flash ADC 100 can be modified so that digital signal y comprises one bit signal.
Implementations of comparators A 102, B 104, and C 106 often use current-mode latch circuits. FIG. 2 is a schematic diagram of an exemplary conventional current-mode latch circuit 200 that can be used in an implementation of any of comparators A 102, B 104, or C 106. Latch circuit 200 comprises a cross-connected pair of transistors 202 connected between a reset switch 204 and first supply voltage VAG 118. Preferably, cross-connected pair 202 comprises a first NMOSFET (n-channel Metal Oxide Semiconductor Field Effect Transistor) xe2x80x9cM1xe2x80x9d 206 and a second NMOSFET xe2x80x9cM2xe2x80x9d 208. Ideally, M1 l 206 and M2 208 are matched transistors. Preferably, each of M1 206 and M2 208 has a gain greater than one. However, cross-connected pair 202 can function if the product of the individual gains of M1 206 and M2 208 (i.e., the loop gain) is greater than one. The gate terminal of M2 208 is connected to the drain terminal of M1 206 at a first port xe2x80x9cN4xe2x80x9d 210. The gate terminal of M1 206 is connected to the drain terminal of M2 208 at a second port xe2x80x9cN5xe2x80x9d 212. The source terminals of M1 206 and M2 208 are together connected to analog ground VAG 118. Preferably, reset switch 204 comprises a third NMOSFET xe2x80x9cM3xe2x80x9d 214. The source terminal of M3 214 is connected to the drain terminal of one of M1 206 or M2 208; the drain terminal of M3 214 is connected the drain terminal of the other of M1 206 or M2 208. A clock waveform xe2x80x9cCkxe2x80x9d 216 is applied to the gate terminal of M3 214. Ck 216 cycles between an xe2x80x9cUPxe2x80x9d voltage and an xe2x80x9cDOWNxe2x80x9d voltage at a sampling frequency.
The skilled artisan will appreciate that M1 206, M2 208, and M3 214 can also be realized in other field effect, junction, or combination transistor technologies. In general, reset switch 204 can be realized in a variety of switch technologies, including microelectromechanical embodiments. Latch circuit 200 can also be used for other applications.
For each latch circuit 200 in ADC 100, quantized signal xe2x80x9cwxe2x80x9d (e.g., w1 132, w2 134, or w3 136) is produced as an output voltage at N4 210 or N5 212. Latch circuit 200 is often preceded by an input stage (not shown) that includes a differential amplifier so that the voltage of analog signal x 128, applied at the noninverting terminal of the comparator, can be compared with the voltage at the inverting terminal of the comparator. For example, the voltage of analog signal x 128 is compared with VDD/4, for comparator A 102; VDD/2, for comparator B 104; and 3VDD/4, for comparator C 106.
For each latch circuit 200 in ADC 100, the input stage produces a differential current signal comprising a first current signal xe2x80x9ci1xe2x80x9d 218 and a second current signal xe2x80x9ci2xe2x80x9d 220. First and second current signals i1 218 and i2 220 each comprise a bias current xe2x80x9cibxe2x80x9d and a signal current xe2x80x9cisxe2x80x9d. The relationship between bias current ib and signal current is in first current signal i1 218 can be expressed as shown in Eq. (1):
il=ib+(1/2)(is),xe2x80x83xe2x80x83Eq. (1)
while the relationship between bias current ib and signal current is in second current signal i2 220 can be expressed as shown in Eq. (2):
i2=ibxe2x88x92(1/2)(is).xe2x80x83xe2x80x83Eq. (2)
The differential amplifier is configured so that first current signal i1 218 increases and decreases in response to, respectively, the rise and drop of the voltage of analog signal x 128, while second current signal i2 220 increases and decreases in response to, respectively, the drop and rise of the voltage of analog signal x 128. Thus, first and second current signals i1 218 and i2 220 always change currents in opposite directions, but the sum of first and second current signals i1 218 and i2 220 remains equal to twice the bias current ib.
For each latch circuit 200 in ADC 100, the differential amplifier is configured so that no signal current is is produced when the voltage of analog signal x 128, applied at the noninverting terminal of the comparator, equals the voltage at the inverting terminal of the comparator. For example, for comparator A 102, no signal current is is produced when the voltage of analog signal x 128 equals VDD/4; for comparator B 104, no signal current is is produced when the voltage of analog signal x 128 equals VDD/2; and for comparator C 106, no signal current is is produced when the voltage of analog signal x 128 equals 3VDD/4.
In latch circuit 200, first current signal i1 218 and second current signal i2 220 are received as input current signals at, respectively, N4 210 and N5 212. When the voltage of Ck 216 is UP (i.e, the reset phase), M3 214 connects N4 210 with N5 212, so that the steady state voltages at both nodes are equal, and bias current ib flows through each of M1 206 and M2 208. Parasitic capacitances at each of nodes N4 210 and N5 212 are charged by bias current ib that flows through each of M1 206 and M2 208. The skilled artisan will appreciate that the parasitic capacitance at, for example, N4 210, includes the gate-to-source capacitance of M2 208, the drain-to-substrate capacitance of M1 206, the drain-to-substrate capacitance of M3 214, and the capacitance of the wiring connecting circuit devices. Bias current ib charges the parasitic capacitances at each of nodes N4 210 and N5 212 so that the voltages at N4 210 and N5 212 are at a metastable xe2x80x9cMIDxe2x80x9d value that is between LOW and HIGH. The gate and drain terminals of M1 206 and M2 208 are connected together. M1 206 and M2 208 are sized so that, under these conditions, they operate in xe2x80x9cONxe2x80x9d states.
When the voltage of Ck 216 is DOWN (i.e., the sampling phase), the states of M1 206 and M2 208 are controlled by first and second current signals i1 218 and i2 220. For example, when first current signal i1 218 is greater than bias current ib and second current signal i2 220 is less than bias current ib, a transient is initiated to force M1 206 to operate in an xe2x80x9cOFFxe2x80x9d state, while M2 208 remains operating in an ON state. The course of this transient depends on how first and second current signals i1 218 and i2 220 change during the sampling phase. If M1 206 is turned OFF and the parasitic capacitances at N4 210 are fully charged by first current signal i1 218 (i.e., at a new steady state), the voltage at N4 210 is HIGH and the voltage at N5 212 is LOW.
It is a characteristic of latch circuit 200 that the port (i.e., N4 210 or N5 212) receiving the current signal (i.e., i1 218 or i2 220) that is greater than bias current ib requires more time to reach its new steady state voltage than the port receiving the current signal that is less than bias current ib. However, if first and second current signals i1 218 and i2 220 both have values near to that of bias current ib (i.e., small signal current is), it is possible that the output voltage (at N4 210 or N5 212) may not reach LOW or HIGH before the end of the sampling phase, but remain in a metastable condition. Such a situation is more likely to occur if Ck 216 cycles at a high sampling frequency. In this situation, the quantized signal (i.e., w1 132, w2 134, or w3 136) produced by the comparator associated with latch circuit 200 (i.e., comparator A 102, B 104, or C 106) does not get registered as a digital input to priority encoder 108. Consequently, ADC 100 does not produce a digital signal y. Such a xe2x80x9cnon-decisionxe2x80x9d is referred to as a xe2x80x9cbit errorxe2x80x9d. Bit errors can adversely effect the performance of a system that uses the digital output of ADC 100.
Bit errors can be reduced by increasing bias current ib so that only a small signal current is is needed to force the port (i.e., N4 210 or N5 212) receiving the current signal (i.e., i1 218 or i2 220) that is greater than bias current ib to reach its new steady state voltage. This increases the overall speed of latch circuit 200. However, increasing bias current ib can decrease the signal-to-noise ratio of ADC 100. Moreover, increasing bias current ib in all of the comparators of ADC 100 causes ADC 100 to dissipate more power, particularly because each comparator draws twice the bias current ib during both the sampling and the reset phases. Such a situation is undesirable where ADC 100 is employed in a system that demands low power consumption, such as a portable wireless application. What is needed is a technique to identify which comparator, in the array of comparators, is in a metastable condition, and to increase the rate at which the identified comparator transitions to a steady state.
The present invention relates to high speed, low power comparators. In an array of comparators, the present invention provides a technique to identify which comparator is in a metastable condition, and to increase the rate at which the identified comparator transitions to a steady state. A bias current is provided to the identified comparator in the metastable condition, such that the rate at which the comparator in the metastable condition transitions to the steady state is increased.
In an embodiment, the bias current is provided by controlling a current output from a variable current source that provides the bias current for a latch circuit of the identified comparator in the metastable condition.
In another embodiment, the comparator in the metastable condition is identified by comparing a characteristic of a first comparator of the array of comparators with a characteristic of a second comparator of the array of comparators. The first comparator and the second comparator are separated in the array of comparators by a third comparator in the array of comparators. It is determined if the third comparator is the comparator in the metastable condition based on the compared characteristics. Preferably, the characteristics are compared by receiving the first and second characteristics as inputs to an Exclusive OR gate.
In yet another embodiment, the bias current is provided by controlling a current output from a variable current source that provides the bias current for a latch circuit of the identified comparator in the metastable condition with an output of an Exclusive OR gate.
In still another embodiment, the bias current is provided by connecting a first current source in parallel with a second current source to increase the bias current for a latch circuit of the identified comparator in the metastable condition. Preferably, a switch that connects the first current source in parallel with the second current source is controlled by an output of an Exclusive OR gate.
The present invention also provides a method to increase, in an array of comparators that includes a first, a second, and a third comparator, a rate at which the third comparator transitions to a steady state. An output of the first comparator is compared with an output of the second comparator, and a bias current is provided to the third comparator based on the compared first and second outputs.
In an embodiment, the outputs are compared by receiving the first and second outputs as inputs to an Exclusive OR gate. Preferably, a variable current source that provides the bias current for a latch circuit of the third comparator is controlled based on an output of an Exclusive OR gate.
In another embodiment, the bias current is provided to the third comparator by connecting a first current source in parallel with a second current source to increase the bias current for a latch circuit of the third comparator. Preferably, a switch that connects the first current source in parallel with the second current source is controlled based on an output of an Exclusive OR gate.
The present invention also comprises an array of comparators comprising a first, a second, and a third comparator, an Exclusive OR gate having a first input connected to an output of the first comparator and a second input connected to an output of the second comparator, and a variable current source connected to an output of the Exclusive OR gate. The variable current source supplies a bias current to the third comparator. Preferably, the output of the Exclusive OR gate produces a signal that controls the variable current source. Preferably, the third comparator is arranged in the array of comparators between the first comparator and the second comparator.
In an embodiment, the third compararator comprises a latch circuit configured to receive the bias current. Preferably, the latch circuit comprises a cross connected pair of transistors connected between a reset switch and a supply voltage. The latch circuit has a first port capable of receiving a first current signal and producing a first output voltage, and a second port capable of receiving a second current signal and producing a second output voltage. In an embodiment, the cross connected pair of transistors comprises a first MOSFET and a second MOSFET configured so that the gate terminal of the first MOSFET is connected to the drain terminal of the second MOSFET, the gate terminal of the second MOSFET is connected to the drain terminal of said the MOSFET, and the source terminals of the first and the second MOSFETs are connected to the supply voltage. Preferably, the reset switch comprises a MOSFET connected between the first port and the second port.
In another embodiment, the array of comparators further comprises a second Exclusive OR gate having an input connected to an output of the third comparator, and a second variable current source connected to an output of the second Exclusive OR gate. The second variable current source supplies a second bias current to the second comparator.
The present invention also comprises an analog to digital converter. The analog to digital comparator comprises an array of comparators, a priority encoder, an array of Exclusive OR gates, and an array of variable current sources. The array of comparators has respective inputs configured to receive an analog signal, and respective outputs configured to produce quantized signals responsive to the analog signal. The priority encoder is connected to the array of comparators, and is configured to produce a digital signal at an output responsive to the quantized signals. Each Exclusive OR gate of the array of Exclusive OR gates is configured to receive two of the quantized signals. Each variable current source of the array of variable current sources is configured to provide a bias current to a corresponding comparator of the array of comparators, and is controlled by an output of a corresponding Exclusive OR gate of the array of Exclusive OR gates.
In an embodiment, each Exclusive OR gate of the array of Exclusive OR gates produces a logic signal that controls a corresponding variable current source of the array of variable current sources. Preferably, each comparator of the array of comparators includes a latch circuit configured to receive a corresponding bias current. In another embodiment, the corresponding bias current is capable of being increased by a corresponding variable current source of the array of variable current sources.
Further embodiments, features, and advantages of the present invention, as well as the structure and operation of the various embodiments of the present invention, are described in detail below with reference to the accompanying figures.